发明名称 BUS CONTROL SYSTEM
摘要 <p>PURPOSE:To enable to decrease the number of external connection pins greatly by inputting microinstructions from a control memory part and transmitting and receiving main memory information and input-output information via the same bus. CONSTITUTION:Arithmetic controller 101, made into one chip of a very high scale integrated semiconductor device, is controlled by external control memory part 102 stored with a microprogram. Then, common bus 103 is provided as a common communication path between controller 101 and an external device and output data of control part 102, memory addresses and memory data of the main memory and I/O data arrive in time-division mode. The number of external connection pins can, therefore, be decreased greatly by transmitting and receiving those signals via bus 103.</p>
申请公布号 JPS5682960(A) 申请公布日期 1981.07.07
申请号 JP19790159486 申请日期 1979.12.08
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 KINOSHITA TSUNEO;SATOU FUMITAKA;YAMAZAKI ISAMU
分类号 G06F13/36;G06F3/00;G06F13/00;G06F13/16;G06F15/78 主分类号 G06F13/36
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