| 摘要 |
PURPOSE:To enable bit-by-bit logical operation as well as word-by-word and byte- by-byte ones, by using and coupling a bus converting circuit, performing bit transmission and reception, with a processor equipped with no bit-by-bit logical operating function. CONSTITUTION:Processor 1 takes instruction INPUTBA1 out of memory device 2 and instructs bus 4 to read data from address BA1 of area 73 accessed, bit-by-bit, in format 7. When the bus converting circuit 6 detects such a read instruction being sent to bus 4, bus converting circuit 6 performs prescribed address conversion to determine assigned addresses and bit positions of input-output devices 32-35 as to area 81 accessed, bit-by-bit, format 8 of bus 5 and sends an input instruction of data D1 to assigned address i/o32. Consequently, input-output device 32 operates as if 8-bit parallel data consisting of D0-D7 were accessed. |
