| 摘要 |
PURPOSE:To reduce the structure of hardware while decreasing the frequency of multiplication by using a recursive digital filter having the transfer relation satisfying specific conditions. CONSTITUTION:Multichannel, e.g. four-channel multiplexed data of sampling rate fSL is inputted to input terminal 1. The input data is supplied to adder 30, whose output is inputted to delay element 50 and multiplier 70. Outputs of delay elements 50-56 are inputted to multipliers 71-77 and those of elements 51, 53, 55, and 57 are inputted to multipliers 60-63, whose outputs are inputted to adder 33 and then supplied to adder 30. Output data of multipliers 70, 72, 74, and 76 are inputted to adder 31, and those of multipliers 71, 73, 75, and 77 to adder 32. Outputs of adders 31 and 32 are both inputted to selecting circuits 80 and 81 and with a timing signal from timing signal generating circuit 9, input signals are selected in time-division mode. Then, two-channel multiplexed signals of sampling frequency fSH=2fSL appear at output terminals 21 and 22. |
