A decoder circuit.

摘要

The decoder circuit has output gates 11a to 11d. Each output gate (11a) has an output driver transistor TW3 for driving an output line (W0). The transistor TW3 is turned ON and OFF in dependence upon the output from a multi-emitter transistor TW1 and TW2 providing a logic AND circuit, which receives address signals A0 and A1. A current switching circuit comprising transistor TW5, inverter transistor TW6 and constant current source 15 is connected to a voltage source line Vcc. Current from the voltage source line Vcc is supplied to the base of transistor TW3 from the current switching circuit when the AND circuit provides a "1" output to inverter transistor TW6. In this way resistor RX is not involved in supply of current to line W0 so that a rise characteristic for that line can be sharpened.