Semiconductor memory array.

摘要

This describes a bipolar semiconductor dynamic RAM cell array in which there is provided a plurality of capacitive storage data cells each being coupled to a respective capacitively loaded bit line and to one another through a common word line. A supply means is coupled to the word line for biasing each cell of the array with respect to its respective bit line to cause the bit line capacitance to set the conductive state of each cell so as to set the respective capacitive storage means of each cell to a selected charge state. The rate at which the storage means of any one cell reaches a selected state is a function of the charge state of any cell, and its respective bit line capacitance, positioned between the selected cell and the supply means.