| 摘要 |
PURPOSE:To give cutback and time delay integration functions, by extending each storage gate to the side of charge transfer elements, providing an input section to one side of the extension of each storage gate via an input gate, and providing the discharge drain at another side via discharge gate. CONSTITUTION:When a signal charge is injected to an input section 10, the injected charge is stored in a storage gate 1 through an input gate 7. When a voltage of 0 volt, e.g., is fed to the bus OFG to close a discharge gate 13 and when the bus TG is set to, e.g., 3 volts, and 01 is set to 7 volts, phi2 to 0 volt, only the charge of effective compoent more than a given level out of the stored charge in the storage gate is transferred to a transfer gate 4b through a transfer gate 4a and to a storage gate 2 of the next stage through a transfer gate 4c further. The charge left in the storage gate 1 is discharged from a discharge drain through a discharge gate 13. |
