| 摘要 |
PURPOSE:To shorten the time of data transfer by setting a reception postponement control line when effective data can not be set up on a data bus within a prescribed time after a transmission-side device sets a data line. CONSTITUTION:When no error is found in read data 13 of main memory unit 2, reception postponement control line 5 is being reset and a microprogram in CPU1 judges that to fetch data on data bus 3. As error code check circuit 11 detects an error in data 13, control line 5 and check error signal line 14 are set. Consequently, error correcting circuit 12, after correcting the error of data 13, outputs the read data to bus 3 and then sets corrected-data reception timing line 7. Circuit 12, when the error can not be corrected, outputs the data 13 to bus 3 as it is and then sets error signal line 8. Then CPU1 fetches data on data bus 3 when line 7 is set and stops the data fetch when line 8 is set. |
