| 摘要 |
PURPOSE:To increase a working efficiency of a memory by inhibiting the transmission of an error signal regardless of existence of the 2-bit error during partial writing, and to detect the error assuredly by inhibiting the writing when the 2-bit error is detected. CONSTITUTION:When the partial write request 117 is given from the CPU9, the F/F14 is set. This set output is supplied to the gate circuit 19 to prevent the transmission of the memory error signal 124 to the CPU9 during the partial writing. As a result, the CPU9 has not to wait for the decision of result of inspection for the reading data, thus increasing the using efficiency of the memory 10. In case the 2- bit error is detected during the partial writing, the error signal 116 is applied to the gate 16 along with the set signal 118 of the F/F14 to set the F/F17. This set output inhibits the data writing to the memory 9. With this inhibition of the writing action, the error factor data remains at the memory. Thus the error is detected assuredly later during the reading. |
