| 摘要 |
PURPOSE:To stably generate timer with an arbitrary delaying time and clock with an arbitrary frequency, by combining the capacity of two capacitors, through the use of two MOSFETs and two capacitors. CONSTITUTION:A node N2 is charged up to the high voltage power supply of IC (not shown). Further, when the clock phicp' is from L to H, a node N1 is at H with the capacity of the capacitor 1. Next, an MOSFET 2 is on and the level of the node N1 is decreased. When the level of the node N1 equals to VTH (threshold voltage of FET2), FET2 is off and the discharge of the node N1 stops. When the clock phicp' is from H to L, the positive charge is moved to the node N1 and FET2 is off. When the node N2 is decreased to VTH, the MOSFET7 is on and the load 6 is driven. Further, with the FET7 turned on, the gate circuit 8 is operated, MOSFET 9 is on and the node 2 is returned to the original voltage level VDD. |
