| 摘要 |
PURPOSE:To accurately and surely detect the lock stat, by digitally processing the phase comparison between the output signal and the input signal of a voltage controlled oscillator of PLL, even if the frequency of input signal is changed. CONSTITUTION:The input signal I of PLL is differentiated at a differentiation circuit 11, a positive pulse is obtained to the leading and trailing of the input signal I at the full wave rectifying circuit 12 from the differentiated pulse, a signal J is obtained by supplying it to the next monostable multivibrator 13 and a pulse P is obtained through the input to the pulse forming circuit 20. The output V of a voltag controlled oscillator of PLL and the pulse P are compared at gates 31, 32, and the PLL is locked, then TFFs 51, 52 are inverted in response to the leading and trailing of the signal J for the outputs A1, A2 of the gates 31, 32, and when the outputs F1, F2 are read in the timing of the signal V at DFFs 61, 62, since the both outputs D1, D2 are always in agreement, no output is producec from an exculsive OR gate 70. When unlocked, the outputs D1, D2 are in disagreement and an output is produced from the gate 70. |
