发明名称 MIS TYPE INTEGRATED CIRCUIT
摘要 PURPOSE:To prevent the generation of potential in the case when releasing a semiconductor substrate to which a plurality of enhancement type transistors are formed by making up a clamp element consisting of a depletion type transistor between a substrate terminal of the substrate and a grounding terminal of a circuit. CONSTITUTION:N<+> type regions 2-8 are diffusion-formed to a P type Si substrate in mutually separating shapes, region 2, 3 sections are used as a transistor Q1 forming a circuit, region 4, 5 sections as a Q3 and region 5, 6 sections as a Q4, and region 7, 8 sections are further employed as a transistor Q5 clamping these transistors. Gate electrodes are each attached to the transistors Q1, Q3, Q4 made up in this manner through gate oxide films, thick oxide films 17-19 for separating elements are made up among the electrodes and the substrate, and a parasitic transistor Q2 is built up under the film 18. A gate electrode 16 of the clamp element Q5 is connected to a substrate terminal 27, and the regions 3, 6 of the elements Q1, Q4 are each connected to a grounding terminal 26.
申请公布号 JPS5673471(A) 申请公布日期 1981.06.18
申请号 JP19800099661 申请日期 1980.07.21
申请人 NIPPON ELECTRIC CO 发明人 KITAMURA YOSHINARI
分类号 H02H7/20;H01L21/822;H01L23/58;H01L27/02;H01L27/04;H01L29/78;H03K19/094 主分类号 H02H7/20
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