发明名称 FAILLSAFE CONSTITUTING METHOD FOR PARALLEL MULTIIINFORMATION SIMULTANEOUS COMPARING CIRCUIT
摘要 PURPOSE:To make it easy to collate arithmetic results of pieces of comparison information by maintaining a fail-safe property easily in fault mode of a constituent element by supervising a rectifying circuit output by magnetic cores having angular hysteresis. CONSTITUTION:To inputs of diode bridges DB of basic detecting circuits 2, pieces of comparison information B1-Bn and M1-Mn are applied being paired to detect the dissidence of information couples. Comparison output line 4 of those detecting circuits 2 is provided with magnetic cores 7 with angular hysteresis as many as information couples to be compared and write line 5 and sense line 6 penetrating those magnetic cores 7 are provided. An output pulse from output line 4 and a negative pulse from write line 5 are supplied as one diagnostic cycle to magnetic core 7 and positive and negative pulse outputs induced at sense line 6 are supplied to two-way shift register 8. The right-left movement of the pulse in shift register 8 is detected by error detecting circuit ED to facilitate the collation of arithmetic results of pieces of comparison information B1-Bn and M1-Mn.
申请公布号 JPS5672747(A) 申请公布日期 1981.06.17
申请号 JP19790148971 申请日期 1979.11.19
申请人 JAPAN NATIONAL RAILWAY 发明人 NAKAMURA HIDEO
分类号 G06F11/18;G06F11/16 主分类号 G06F11/18
代理机构 代理人
主权项
地址