| 摘要 |
<p>PURPOSE:To make it possible to make even signal width among phases in width by generating a polyphase synchronizing signal at each processor by using a basic clock supplied from a common signal generator and an interdevice synchronizing signal. CONSTITUTION:Signal generator 1 sends a clock signal from a pulse oscillator to processors 2 and 3 as a basic clock via respective gates. Further, the clock signal is sent to processors 2 and 3 as an interdevice synchronizing signal by way of the delay element, counter, and AND circuit. In processors 2 and 3, the basic clock from generator 1 is supplied to trigger terminal T of FF21 and the interdevice synchronizing signal to reset terminals R of FFs 21 and 24. Then, two-phase clocks can be obtained from FFs 22 and 24 and a four-phase synchronizing signal can be generated from those two-phase signals. Thus, the signal width among phases can be made even by processors 2 and 3.</p> |
