发明名称 PREPARATION METHOD OF SEMICONDUCTOR SYSTEM
摘要 PURPOSE:To obtain an FET having a short gate by a method wherein using two resist walls each of which is close to each other and selecting a proper evaporation angle, an electrode is formed. CONSTITUTION:A mesa type N epitaxial layer 7 is installed on a semi-insulating GaAs substrate 6, and resist walls 8, 9 which are extending to a direction are formed making each of them be close to each other. Since the surface is flat and smooth, working of a micro pattern of approximately 1mum can be easily performed. An ohmic metal for the electrode use is vapored from a slant 2 directions and source and drain electrodes 10, 11 are installed. And next thereto, Al and others for the Schottky barrier forming use is vapored to the substrate principal surface from a vertical direction to form a gate electrode 12 on an operation layer 7 between the walls 8 and 9. The resists 8, 9 are removed and a heat processing is performed to form a good ohmic electrode. With this constitution, by means of a self matching, an FET having an extremely short gate length is obtained with a good yield.
申请公布号 JPS5671981(A) 申请公布日期 1981.06.15
申请号 JP19790149818 申请日期 1979.11.19
申请人 SUMITOMO ELECTRIC INDUSTRIES 发明人 OOTANI SHIYUNJI;KIKUCHI KENICHI
分类号 H01L21/28;H01L21/338;H01L29/417;H01L29/80;H01L29/812 主分类号 H01L21/28
代理机构 代理人
主权项
地址