| 摘要 |
PURPOSE:To compensate a phase difference which is up to twice a frame length at a maximum or a half at a minimum, by forcing a flip-flop, controlling the operation of a register for information transfer to be in state [ready] or [busy]. CONSTITUTION:In the frame-synchronism break state, receiver 6 sends a synchronism break signal to counter 7. Then, counter 7 is reset, but continues to send an on signal to line 31 until it reaches a set value. Consequently, gates 10 and 14 are opened. In this state, counter 8 is put into operation to output the signal, holding FF12 in readiness, to signal line 28 at the point in time when it counts up a half as much as the frame length. Frame bits from sugnal lines 27 are inputted to FF12 and if any pulse does not appear at signal line 34 even after the counter's value exceeds the half of the frame length from busy state 30, signal line 28 is forced to be in the ready state. |
