| 摘要 |
PURPOSE:To reduce switches in number by comparing plural potentials, obtained by dividing a reference voltage, with an input voltage in sequence, by ORing comparison outputs with a clock and by inputting OR outputs to a conter. CONSTITUTION:Flip-flops 22-24 are reset, transfer gate 11 conducts and V1 obtained by dividing reference voltage VR and input signal VI(1) are compared by comparator 17. When input signal VI(1) is greater, clock CL1 passes through gate 20 and is applied to counter 21. Next, V2 and VI(1) are compared and according to the comparison result, counter 21 counts up. Namely, at the point in time when comparions reference voltage VI(2) exceeds VI(1), counter 21 stops the counting and the digital value that corresponds to input signal VI(1) can be obtained. |
