| 摘要 |
PURPOSE:To realize the low power consumption without lowering the velocity of the circuit operation for an asynchronous complementary MIS memory circuit, by using the MISFET serial circuit of the n and p channels for the load circuit of the data line. CONSTITUTION:For the load circuit of the data line D of the complementary MIS memory circuit of the asynchronous type (full static type) which forms the memory cell, a serial connection is secured among the n channel FETQ7 and Q8 having a connection between the gate and the drain to obtain the output from the source plus the p channel FETQ11 and Q12 via the complementary flip-flop circuit of the n channel MISFETQ1 and Q2 plus the p channel MISFETQ3 and Q4 each. Thus each load circuit is obtained for the line D. As a result, the load circuit shows the constant current properties to give a limitation to the flowing current. |
