发明名称 Division processing method system having 2N-bit precision
摘要 A division processing system performs 2N-bit precision division processing by effectively using division processing circuitry with N-bit precision. The system performs the division with 2N-bit precision as follows: <IMAGE> (n=N: the number of digit positions in selected binary numbers A, B, C and D). The above expression is approximated to the form of Q1+Q2x2-n (Q1, Q2: binary numbers). The binary numbers Q1 and Q2 are respectively operated on by the division processing circuitry with N-bit precision. By effective control, the error caused during the division processing of Q1 is used as a part of the data for performing the division processing of Q2, thus effectively transferring any error evolving during the processing of Q1 to Q2. The function is performed in a system having only four registers, each of N-bit capacity (precision), and an operation register, multiplication circuitry, division circuitry, and a shift circuit, affording proper control of data transfer between the registers.
申请公布号 US4272827(A) 申请公布日期 1981.06.09
申请号 US19790021011 申请日期 1979.03.16
申请人 FUJITSU LIMITED 发明人 INUI, NORIO;KUME, NORIAKI;OKAMOTO, TETSURO
分类号 G06F7/52;G06F7/527;G06F7/535;(IPC1-7):G06F7/52 主分类号 G06F7/52
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