| 摘要 |
PURPOSE:To eliminate the operation of the modulo (n) for the output access and thus realize a high-speed operation for the shift register which performs a shift by an address operation and via a large-capacity RAM, by providing the K-bit counter as a pointer. CONSTITUTION:The data to be shifted to the large-capacity RAM20 of 2K words is written through the latch circuit 21 and in synchronization with the clock CLK. The address of this instant is formed by adding through the adder 24 and with K bits the contents of the K-bit counter 23 which performs a count-down to the contents obtained by latching the shift amount data through the latch circuit 22 and by the address strobe signal ADRSTB. The circuit 22 is cleared CLR with every clock, and the shift amount data is latched only when the shifted data is read out. Then the contents of the counter 23 at that moment and the added contents form the address which is read out of the RAM20. |
