| 摘要 |
PURPOSE:To prevent unequality of a cell capacitance by a method wherein a separating gate is used to separate a word line of an MOS dynamic RAM from a memory cell and an MOS capacitance is constituted with the 2nd layer polysilicon gate. CONSTITUTION:An 1-transistor 1-capacitor type memory cell consists of an N<+> diffusion area 11 constituting a bit line, the 1st layer polysilicon gate 12 constituting a word line, a separating gate 16 wherein a VSS voltage is applied to separate each memory cell one another, the 2nd layer polysilicon gate 13 constituting an MOS capacitor and a gate oxide film 14. And during the 1st layer polysilicon gate being formed, each of the gate are of a transfer transistor, the area of an MOS capacitor and the area of an N<+> diffusion layer is decided and they are equal without depending upon an error of a mask matching, thus, resulting in each equal cell capacitance and each equal bit line capacitance. |
