发明名称 LOGIC CIRCUIT
摘要 PURPOSE:To operate the titled circuit at the maximum operating frequency by connecting an inverter comprising depletion/enhancement type Schottky FETs at the post-stage of a noninverted buffer. CONSTITUTION:With an input at a high level, because a Schottky FET is employed for a FET Q2, the high level is clamped by the forward voltage of the diode. Since the gate voltage of the FET Q2 of the push-pull stage is also clamped in this way, the FET Q3 cannot turn on the FET Q6 of the next stage. The source potential of the FET Q3 cannot be at a high level because the input potential C is clamped, then the FET Q6 cannot be turned on and the drain voltage B of the FET Q6 cannot be decreased to the low level.
申请公布号 JPS6454927(A) 申请公布日期 1989.03.02
申请号 JP19870212287 申请日期 1987.08.26
申请人 TOSHIBA CORP 发明人 SHIMIZU SHOICHI
分类号 H03K19/0944;H03K5/15;H03K5/151;H03K19/094 主分类号 H03K19/0944
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