发明名称 BUFFER MEMORY UNIT
摘要 PURPOSE:To perform efficient block disconnection during error detection by providing a swap-system buffer memory unit with a row contracting method that indicates that block (BL) has been disconnected within rows assigned by address BL and a column contracting method that indicates that BL has been disconnected within columns assigned by set addresses. CONSTITUTION:The swap-system buffer memory unit is provided with column contracting display circuit 71 and set contracting display circuit 72. While data are being read out of the 1st or 2nd buffer memory part 11 or 12, error detecting circuit 61, when detecting an error, sets 1 to a column contraction bit in column display circuit 71 determined unconditionally by a signal from decoder 33 and also sets 1 to a contraction display bit in set contracting display circuit 72 by the outputs of comparing circuits 51 and 52, thereby registering the blcok, which was being read at th time of the error detection, as a disconnected block through gate circuit 73 and 74, and the substitute control circuit. Consequently, efficient block disconnection can be performed during error detection with small hardware.
申请公布号 JPS5665381(A) 申请公布日期 1981.06.03
申请号 JP19790138485 申请日期 1979.10.26
申请人 NIPPON ELECTRIC CO 发明人 NISHIOKA HIROSHI
分类号 G06F12/12;G06F13/00 主分类号 G06F12/12
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