发明名称 PILOT SIGNAL DETECTING SYSTEM
摘要 PURPOSE:To simplify the constitution as well as reduce the power consumption, by integrating the output of the voltage comparator and then performing a detection with the fixed identification level after a detection with the identification level different from the fixed identification level or after a fixed time. CONSTITUTION:The pilot signal and the modulated frequency signal are supplied to the exclusive logic sum circuits 61, 62 and 63 each, and these outputs are supplied to the voltage comparators 64, 65 and 66 via the low-pass filters L1, L2 and L3 each. The outputs of comparators 64, 65 and 66 vary at the moment when the pilot input signal is erased, and then supplied to the circuits 67, 68 and 69 each which perform an integration and level identification.
申请公布号 JPS5664529(A) 申请公布日期 1981.06.01
申请号 JP19790140077 申请日期 1979.10.30
申请人 FUJITSU LTD 发明人 KAMEI SABUROU
分类号 H04B17/00;H04B3/10 主分类号 H04B17/00
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