发明名称 ASYNCHRONOUS COMMUNICATION SYSTEM
摘要 <p>PURPOSE:To realize assuredly the setting of the clock for a start-stop synchronous receiving circuit with a simple circuit constitution, by producing the data of 1-bit width at the transmission side and then measuring the time duration at the reception side respectively. CONSTITUTION:The input data having the time duration equivalent to the start bit is supplied through the transmission line 1 and in the form of the received data. This data is sampled through the sampling circuit 2, and the output of this sampling circuit 2 is supplied to the counter 3. Then the clock selection circuit 4 sets the input clock of the start-stop synchronous receiving circuit 5 in a correct way according to the value of the counter 3.</p>
申请公布号 JPS5664541(A) 申请公布日期 1981.06.01
申请号 JP19790140080 申请日期 1979.10.30
申请人 FUJITSU LTD 发明人 HASHIMOTO MASAMICHI;ARITAKA TOKUHIRO;TSURUMAKI SHINZOU
分类号 H04L7/04;H04L25/24 主分类号 H04L7/04
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