发明名称 |
DC motor fault monitoring circuit - has tachogenerator connected to adder and two comparators connected by gate to flip=flop |
摘要 |
<p>The fault monitoring system for a d.c. motor includes a tachogenerator (TG) coupled with the motor (DCM). A control signal (SPC) is applied to an adding stage (AD) connected by an amplifier (AMP) with connections across the motor. The tachogenerator is connected back to the adder. A reference signal (A) is applied to the motor with a connection (Vr1) to a comparator (CMP1) and a signal (B) corresponding to the motor speed is connected to a second comparator (COMP2). Both comparators are connected by a gate (G1) to a flip flop (FF1). When a fault is indicated by the tachogenerator, an alarm signal is given by the flip flop. The system can be used for a motor rotated in either direction.</p> |
申请公布号 |
FR2470475(A1) |
申请公布日期 |
1981.05.29 |
申请号 |
FR19790028443 |
申请日期 |
1979.11.19 |
申请人 |
FUJITSU FANUC LTD |
发明人 |
SHIGEKI KAWADA, KATSUO KOBARI ET HIROSHI ISHIDA |
分类号 |
H02H7/093;(IPC1-7):02P5/06 |
主分类号 |
H02H7/093 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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