| 摘要 |
A circuit arrangement is provided for identifying an alignment word of m bits from a demultiplexer DM of a digital communication system having n channels. The circuit arrangement Fig. 2 (not shown) includes a memory comprising n shift registers of length (n + m)/n for receiving n bit flows from the demultiplexer DM. A decoder DC energizes one of its n outputs according to the way in which the bits of the alignment word have been distributed in the shift registers of the memory. A coder CM provides a code q corresponding to the energized output, where n</=2<q>, and supplies this code as a control signal to an exchange matrix MS which reorganizes the n bit flows, if necessary, into n bit flows of the n channels. Thus, the demultiplexer output is aligned by the circuit arrangement, which is only required to operate at 1/n times the speed of the demultiplexer. <IMAGE> |
