| 摘要 |
1,258,632. Digital processors. HONEYWELL Inc. 13 Jan., 1969 [29 March, 1968], No. 1975/69. Heading G4A. For diagnostic purposes the parity bit of a word to be read in to the store of a processor can be inverted to distinguish the word. The circuitry described provides, under selectable conditions, stop or synchronizing signals on detection of inverted parity in a word read out. The store comprises a core matrix memory 10 from which a word is read via units 14, 30 to register 16 and check unit 31. The latter derives a parity bit which is compared at 32 with the parity bit in 34 from the word read out. Register 16 passes the word read out to the store 10 via units 15, 12. Unit 17 generates a parity bit for this word, the bit being passed to gate 37 in true or inverse form as selected by switch 46. If a comparator 32 shows a parity error, subsequent action depends on the position of switch 46. If switch arm 48 is as shown, gate 35 outputs during Read, if the arm is on C gate 50 outputs during Write, and if the arm is on B gate 51 outputs during Read and Write. The output of these gates passes either via gate 61 or gate 62, dependent on switch 60, to provide a pulse which stops operation so that the point in the program at which the stop occurs can be assessed, or to provide a sync. pulse to a c.r.t. which displays the electrical conditions occurring in a memory loop set up after faulty operation has been detected to produce the fault signal repeatedly. |
