| 摘要 |
PURPOSE:To make available high speed operation by a method wherein, when preparing a vertical type MOSFET, impurity concentration of a gate is made lower than that of a drain to advance the expansion of a depletion layer due to a drain bias and shorten the effective gate width. CONSTITUTION:An N type layer 10 used as a drain region is formed by diffusion on the rear surface of a P type Si substrate 9 to be used as a gate region, while an N type source region 11 is provided on the surface of the substrate 9. Next, a V-shaped groove 12 is made in such a way that it penetrates from the central portion of the region 11 into the layer 10, and the walls are covered with a gate oxidized film 13 on which a gate electrode 15 is attached. In addition, a ring-shaped source electrode 16 is located on the boundary between the region 11 and the substrate 9, and the connecting ends 17 of the substrate 9 and the layer 10 are mesa- processed, while a drain electrode 16 is attached to the rear surface of the layer 10. By so doing, it becomes possible to advance the depletion layer toward the substrate 9 because the concentration of impurities in the substrate 9 is lower than that of the layer 1. The gate travelling time of the carrier is shortened, thus making high speed operation available. |
