| 摘要 |
<p>The invention provides a circuit for converting M-bits of an input data word having M + A bits in addition to an input parity bit, to B-bits of an output data word having B + A bits in addition to an output parity bit. A code-conversion circuit is responsive to the input M-bits for generating a converted data word having B-bits plus a secondary parity bit which gives the converted data word a parity value the same as that of the input M-bits. The secondary parity bit is exclusive-ORRED with the input parity bit to produce an output parity bit which renders the parity value of the output data word the same as that of the input data word. - i</p> |
