发明名称 MANUFACTURE OF MOS INTEGRATED CIRCUIT OF MUTUAL COMPENSATION TYPE
摘要 PURPOSE:To eliminate a cavity and improve the yield by a method wherein two thin multicrystal Si layers are employed, the ion is implanted through these layers to form a diffused region and also the resistance value of the multicrystal Si layers are lowered in the manufacture of C-MOSIC wherein the multicrystal Si is used for a gate electrode. CONSTITUTION:A P<-> type region 16 is formed diffusely on an N type Si substrate 15 and in the part around the region 16 and on the surface apart therefrom a thick field oxide film 17 is provided, while on the surface surrounded thereby a thin gate oxide film 18 is fitted. Next, a window is opened in a prescribed position of the film 18, a multicrystal Si layer 19 and a thin multicrystal Si layer 20 are laminated and piled on the whole surface, the region 16 is covered with a mask of SiO2 film 21, ions of impurities are injected and later heat treatment is applied, and thus a P<+> type region 22 is formed within the substrate 15 on both sides of the remaining film 18. After that, the film 21 is removed, a mask of SiO2 film 23 is provided on the region 22, ions are implanted in the same way as the above to form an N<+> type region 24 within the region 16, while an electroconductivity is given to the layers 19 and 20 respectively.
申请公布号 JPS5656676(A) 申请公布日期 1981.05.18
申请号 JP19790132595 申请日期 1979.10.15
申请人 SUWA SEIKOSHA KK 发明人 ICHIKAWA MATSUO
分类号 H01L27/092;H01L21/28;H01L21/8238;H01L29/78 主分类号 H01L27/092
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