发明名称 MEMORY CONTROL SYSTEM
摘要 PURPOSE:To improve the processing efficiency of the whole system by storing a fault when the fault is detected by access from one access unit in case that one memory unit is shared among plural access units, and then by inhibiting access to a fault area according to the memory contents. CONSTITUTION:Processors 5 and 6 are provided with internal-circumference reading circuit 9 and outer-circumference reading circuit 10 for magnetic disk device 8 to attain access to device 8. Further, processor 5 is provided with error detecting circuit 20, AND gate 13 and FFs 11 and 12. Once an error is detected by circuit 20, the operation of circuit 9 is stopped via line 15 and then circuit 10 is actuated to set FF11. Further, as a reading of the outer circumference area is normally finished by circuit 10, circuit 20 sets FF12. Next, when processor 6 is put into operation, a reading of the inner circumference by circuit 9 of processor 6 is stopped with the output of gate 13 and a reading of the outer circumference is taken by circuit 10, improving the processing efficiency of the system.
申请公布号 JPS5654557(A) 申请公布日期 1981.05.14
申请号 JP19790128946 申请日期 1979.10.08
申请人 HITACHI LTD 发明人 KANEKO HIDEKAZU;KUNO KIYOSHI
分类号 G06F12/16;G06F3/06;G06F13/00;G11C29/00 主分类号 G06F12/16
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