| 摘要 |
<p>A Schottky collector transistor (PNM) inverter circuit is used to implement a positive logic, multiple input, single output NAND gate or a single input, multiple output NOR gate. The NAND function is achieved by merging two PNM inverters in a common emitter configuration, such that the common emitter also comprises the base of a dual collector NPN load transistor, and each PNM base comprises an NPN collector. Circuit densities are approximately double the densities of comparable I<2>L configurations, Both speed and speed-power product are improved over conventional I<2>L.</p> |
