Serial-parallel-serial CCD memory system with fan out and fan in circuits.

摘要

An SPS Serial-Parallel-Serial charge coupled device (CCD) memory system is provided wherein a single tap, preferably a storage node, on an input serial or shift register (10) is connected to the input of a plurality of parallel shift registers (14) through a fan out circuit (D) and the output of the plurality of parallel shift registers is connected to a single tap, preferably a storage node, on an output serial or shift register (12) through a fan in circuit (E).