发明名称 PREPARATION OF SEMICONDUCTOR DEVICE
摘要 PURPOSE:To permit the alignment accuracy needed for two or more photolithographic processes to be reduced by using the pattern portion formed by composing two patterns crossing each other as a pattern for a photolithographic process. CONSTITUTION:Resist 4 as the first layer is applied, and a pattern 5 for metal wiring is formed on a diffused layer 6. Then resist 7 as the second layer is applied, and a pattern 8 crossing the pattern 5 is formed. A pattern portion 9 formed by composing the patterns 5 and 8 is used as a pattern for contact hole. This eliminates the need for the accuracy of the alignment vertical to the metal wiring as well as the need for allowance on the pattern. Then a film 10 under the pattern portion 9 is etched to make a contact hole. The resit 7 is removed, and a metal wiring 11 is formed by the lift-off method using the resist 4.
申请公布号 JPS5651827(A) 申请公布日期 1981.05.09
申请号 JP19790128542 申请日期 1979.10.05
申请人 SUWA SEIKOSHA KK 发明人 HOSHI JIYUNICHI
分类号 H01L29/78;G03F7/20;H01L21/027;H01L21/28;H01L21/30;H01L21/768;H01L23/522 主分类号 H01L29/78
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