发明名称
摘要 <p>Input/output registers integrated with logic and arithmetic circuits are combined externally of a processor nucleus having only storage registers, instruction decode logic, timing circuitry and arithmetic and logic unit for executing microinstructions whereby the use of the input/output registers is determined by microprogram code and by time control to either selectively execute all adapter and interface communication and control functions for input and output devices or to selectively be switched into the data flow of the processor nucleus.</p>
申请公布号 JPS5619650(B2) 申请公布日期 1981.05.08
申请号 JP19750092645 申请日期 1975.07.31
申请人 发明人
分类号 G06F9/22;G06F13/12;G06F13/14;G06F15/16;G06F15/78 主分类号 G06F9/22
代理机构 代理人
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