| 摘要 |
PURPOSE:To perform the test for operating life time in the form of a wafer with ease by a device wherein a pair of common power source lines are provided at the periphery of a semiconductor wafer including a plurality of IC chip areas formed in line. CONSTITUTION:A plurality of IC chip areas 1 are formed on a semiconductor wafer 7 in the square form with dicing areas 2 therebetween and a pair of power source lines 3 and 4 are continuously formed at two parallel sides of each area 1 extending at right angles with the areas 2. Then, thus arranged areas 1 are formed on the wafer 7 by the predetermined number and a pair of power source terminals 5 and 6 at right angles with the lines 3 and 4 on the peripheral edges of the wafer 7 facing each other. The lines 3 and 4 are respectively connected to the terminals 5 and 6 alternatively. By so doing, all areas 1 can be tested at the same time by applying the source voltage for a test of operating life time only on the paired terminals 5 and 6, so that the test is carried out with high efficiency. |
