| 摘要 |
PURPOSE:To make it possible to eliminate a chattering noise securely by resetting two FFs by detecting dissidence between two FF outputs by exclusive OR with a clock signal at constant intervals of time. CONSTITUTION:When a chattering noise is inputted to inputs S of FFs 13A and 13B having been preset yet, logic L of the input component holds both outputs Q of FFs 13A and 13B at logic H and output 16 of gate 14 at logic L. When there is no noise, on the other hand, one output Q is at logic H, and the other at logic L, generating output 16 of logic H. In this case, gate 25 outputs signal 15 as output signal 17. Since signal 16 has logic L while the noise is generated, logic L from gate 25 is outputted as it is. Output 17 is fetched into FF24 at the rise of output clock 18 of oscillator 20 and then latched. Then, FFs 13A and 13B are reset immediately by MM22. Output 19 of FF24 generated as mentioned above is shown in the figure and the noise removed. |
