发明名称 DATA PROCESSOR HAVING COMMON MONITORING AND MEMORY LOADING AND CHECKING MEANS
摘要 In order to make internal states within a digital data processor (10) more readily accessible, upon interruption of the normal operation thereof for monitoring purposes, the digital data processor is provided with variable mode multi-bit shift register storage devices (15) which store such states which are made accessible using controllable gates (G1) to form separately selectable serial strings which permit the states stored in a selected string to be serially shifted to a monitoring unit (20) for monitoring, diagnosing and/or correcting purposes and then returned, via the string, to their original locations in the storage devices. By also using the string connectable variable mode multi-bit shift register devices as input-output registers of one or more micro-code storing RAMS (random access memories M1-Mn) in the data processor, the internal micro-codes may similarly be monitored as well as changed by also using the strings to load the RAMS with new or changed micro-codes.
申请公布号 WO8101208(A1) 申请公布日期 1981.04.30
申请号 WO1980US01376 申请日期 1980.10.14
申请人 BURROUGHS CORP 发明人 DAVIS S;FRANKS R;DESANTIS A
分类号 G11C29/00;G06F11/22;G06F11/267;G06F11/273;G06F11/30;G06F12/16;G11C29/32;G11C29/56;(IPC1-7):06F11/00;06F15/00;06F9/22 主分类号 G11C29/00
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