发明名称 PARITY CHECK SYSTEM
摘要 PURPOSE:To make it possible to perform the parity check and generate the parity easily and efficiently, by using as time division a parity circuit provided on the output side against input/output data of the logical operation circuit (ALU). CONSTITUTION:When input data A, B are transferred to ALU11 by the timings (a), (b), the operation control circuit 12 generates a control signal CNT by which a data A is made an output data as it is, at first, and the parity circuit executes the parity check to the output data A. Subsequently, the control cirucit 12 controls the input data B so that it can be output, executes the parity check in the same way as the foregoing, after that, operation processing of the input data A and B is executed to ALU11 from the operation control circuit 12, and the result F is output as an output data. The parity circuit 13 adds a parity bit to its output data.
申请公布号 JPS5647846(A) 申请公布日期 1981.04.30
申请号 JP19790123708 申请日期 1979.09.26
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 YAMAGUCHI TAKAYUKI
分类号 G06F11/10 主分类号 G06F11/10
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