发明名称 ARITHMETIC UNIT
摘要 PURPOSE:To release an input data line and make it possible to perform the operation or processing by other operator in parallel, by latching an input data. CONSTITUTION:The microinstruction for designating the operation of a multiplier 12 is set to the register 20. An operation data is provided to the buses 10 and 11 by a control signal from the control part 17. This data is latched to the data latch circuits 15, 16. While the data is being latched, the operation designated from the control part 17 is executed. On the other hand, while the data is being latched by the latch circuits 15, 16, the buses 10, 11 are released, and when the operation designating instruction of the arithmetic unit (ALU) 13 is set to the register 20 before execution of the aforesaid operation is finished, ALU13 executes this operation. Thus, the parallel operation can be performed.
申请公布号 JPS5647840(A) 申请公布日期 1981.04.30
申请号 JP19790124221 申请日期 1979.09.28
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 MIYATA MISAO;OOHASHI MASAHIDE
分类号 G06F7/00;G06F7/38 主分类号 G06F7/00
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