| 摘要 |
This relates to an expandable arithmetic logic unit (ALU) capable of performing binary and BCD addition and subtraction and various logic transfer functions in no more than four stages of logic delay from data input to ALU output. Propagate and generate signals (Pi and Gi) are produced in a single stage of delay and are applied to group propagate and generate logic. The group propagate and group generate signals are produced in a second stage of logic delay and are utilized to form carry look-ahead signals in a third stage of logic delay. Additional logic produces the required logic transfer signals (Hi) one logic delay after generation of the individual Pi and Gi terms. The carry look-ahead signals and logic transfer signals are combined to produce the ALU output.
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