| 摘要 |
PURPOSE:To reduce noise after locking and to decrease the lockup time by selecting the quantity of the drive capability and outputting the result in detecting the unlock state or lock state of the PLL. CONSTITUTION:When a PLL lock detection circuit 26 detects the unlock state of the PLL, a changeover circuit 27 selects and outputs an output signal of large drive capability in 1st and 2nd pre-stage signal transmission circuits 22, 24 and 23, 25 and outputs an output signal with a small drive capability in detecting the lock state of the PLL. Thus, in case of the lock state, the gain constant of a phase detection circuit phi-DET 1 including the charge pump circuit 21 is small and the gain constant in the unlock state is large. Thus, the lockup time of the PLL is short in the unlock state and the noise of the PLL system is reduced in the lock state. |
