| 摘要 |
PURPOSE:To eliminate the data reading mistake, by selecting automatically one phase out of the n-phase clocks which are roughly synchronized with each other and then using the phase as the optimum phase clock. CONSTITUTION:The clocks phi1-phin are obtained by dividing one data bit time into n phases, and only one-phase clock is selected by the switches SW1-SWn among those clocks phi1-phin. And this selected clock phiout is delivered to the reader 1. If some mistake is detected for the data which is read in with the clock phiout used as the clock, this mistake is detected by the data reading detector 2. And this detection output actuates the switch control circuit 3 to change the switch turned on, and thus an automatic scanning is continued until the clock phiout which is read correctly is obtained. Here the detector 2 detects the mistake by the output of the parity check or the check of the continuous sending of the reading data. |
