| 摘要 |
PURPOSE:To simplify a 2-bus constitution system and to improve data transfer efficiency by performing the direct transfer of data between an input/output interface and a memory connected to the two buses respectively. CONSTITUTION:A bus right control means 80 has the using right requests for buses 30 and 40 under the control decided by an action deciding means 73. At the same time, the data and address transmitting directions are controlled by direction control means 51a, 51b, 52a and 52b and 83. In addition, the interruptions to a slave control part 74 and an interruption control part 92 and the accesses given from these parts are controlled by both parts 74 and 92 serving as the interruption and access control means respectively. As a result, the direct transfer of data is possible between the I/O interfaces 32 and 42 and memories 33 and 43 which are connected to the buses 30 and 40 respectively. In such a constitution, an FIFO and its peripheral circuits can be omitted so that the constitution of a DMA controller is simplified together with improvement of the data transfer efficiency. |
