| 摘要 |
PURPOSE:To attain the processing time at high speed by executing in parallel a first subtraction to subtract the absolute value of a second operand from the absolute value of a first operand and a second subtraction to subtract the absolute value of the first operand from the absolute value of the second operand. CONSTITUTION:A first subtracting circuit 11 subtracts an absolute value 13 of a second operand from an absolute value 12 of a first operand, generates a first difference 14 and simultaneously, by the subtraction, a carrying signal 15 to show whether or not the overflow occurs is generated. A second subtracting circuit 16 subtracts the absolute value 12 of the first operand from the absolute value 13 of the second operand and generates a second difference 17. A first selecting circuit 23, when a carrying signal 15 shows that the overflow does not occur, selects the first difference 14, and when the signal shows that the overflow occurs, the second difference 17 is selected and outputted. |
