| 摘要 |
1309139 Semi-conductor devices SONY CORP 25 Sept 1970 [29 Sept 1969] 45827/70 Heading H1K [Also in Division H3] Adjacent transistors M 3 of a plurality of delay flip-flop memory circuits (Fig. 5, not shown) comprising MIS transistors formed on a common substrate have drain and source electrodes Db, Sb, Dc, Sc formed with P-type layers in N-type substrate 2; an oxide insulant layer Cb overlying Db, Sb with gate Gb thereon, and an oxide insulant layer Cc overlying Dc, Sc with gate Gc thereon. A thicker insulant layer C2b, C2c is formed on the substrate intermediately of Cb and Cc to reduce the mutual conductance of the parasitic transistor Mb, Mc (Fig. 7, not shown) and is overlain by lead 3b interconnecting the gates to a clock pulse, and parasitic interaction leading to readout loss is prevented by a P-type layer 5 formed in the substrate intermediately of Sb and Sc simultaneously with the formation thereof; with an electrode 4 deposited thereon and connected to lead 3b. The drain and source are interchangable, and the memory circuit is described in detail. Specification 1,290,149 is referred to. |
