| 摘要 |
Disclosed is a circuit for restoring charge to the cells of a semiconductor memory during a read operation. A respective one of the circuits couples to each of the bit lines of the memory. No power is dissipated in those circuits which couple the bit lines that are to be discharged during a read. Also, the circuit includes only three transistors, and thus occupies a minimal amount of chip space. In addition, the circuit is operable in response to only a single clocking signal. Further, the circuit is operable over a relatively large range of precharge voltage levels for the bit lines such as 3 volts to 7 volts.
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