| 摘要 |
PURPOSE:To detect an error of an address selective matrix circuit by determining a parity bit in data write operation in connection with an address signal and by making a parity check in read operation in connection with the address signal. CONSTITUTION:To exclusive-OR circuit 6, parity bit P2 added to address signal ROMA of ROM1 and parity bit P0 of data ROMDT written at an address part indicated by signal ROMA are transferred. Output signal P0 of circuit 6 obtained on the basis of those bits P0 and P2 and data signal RDT outputted from ROM1 on the basis of signal ROMA are supplied to check circuit 7 to make a parity check. Further, signal ROMA is checked in terms of parity by check circuit 3 with parity bit P2. |
