发明名称 LOGICAL INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To reduce a reactive current and heighten the density of integration, by providing the collector and base of a horizontal bipolar unit of SITL and the gate and source of a vertical SIT as common regions and placing the emitter of the bipolar unit so that the emitter is surrounded by the gate. CONSTITUTION:An inverted vertical SIT is composed of an N<+> type source 12, an N<-> type channel 13, a P<+> type gate 14 and N<+> type drains 11a, 11b. A horizontal bipolar unit is composed of a P<+> type emitter 15, an N<-> type base 13a and a P<+> type collector 14. The P<+> type emitter 15 is surrounded by the P<+> type gate 14 together with the interposed N<-> type base 13a in the same manner as the N<+> type drain 11a is surrounded. According to this constitution, almost all of positive holes injected through the side faces and bottom of the P<+> type emitter 15 reach the P<+> type gate 14 to reduce a reactive current.
申请公布号 JPS5636156(A) 申请公布日期 1981.04.09
申请号 JP19790111568 申请日期 1979.08.31
申请人 SEIKO INSTR & ELECTRONICS;HANDOTAI KENKYU SHINKOKAI 发明人 NISHIZAWA JIYUNICHI;TANAKA KOJIROU
分类号 H01L21/8222;H01L21/331;H01L27/02;H01L27/06;H01L29/73;H03K19/091 主分类号 H01L21/8222
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