DUAL CHANNEL SIGNAL DETECTOR CIRCUIT

摘要

DUAL CHANNEL SIGNAL DETECTOR CIRCUIT A dual channel signal detector circuit comprising an equalizer for responding to a variable peak amplitude input signal, in which the peaks are representative of data, so as to provide a substantially constant peak amplitude output signal having discrete data representative pulses spaced along a base line, which is substantially flat at the zero level in regions intermediate the pulses, for application to separate peak detection and amplitude detection channels. The peak detection channel produces data pulses each indicative of the relative time occurrence of the peak of a respective data representative pulse while the amplitude detection channel is triggered by signal levels of the data representative pulses exceeding a predetermined threshold to produce gating pulses for gating the data pulses to the circuit output substantially exclusive of any noise that may be present at the input of the circuit.